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MC68HC05C9E
Advance Information Data Sheet
M68HC05 Microcontrollers
MC68HC05C9E Rev. 0.1 9/2005
freescale.com
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
Blank
MC68HC05C9E
Advance Information Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date September 2005 Revision Level 0.1 Description Updated to meet Freescale identity guidelines. Page Number(s) Throughout
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 3
Revision History
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 3 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Chapter 6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Chapter 7 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Chapter 8 Capture/Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chapter 9 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 11 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chapter 12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Chapter 13 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Chapter 14 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Appendix A Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Appendix B M68HC05Cx Family Feature Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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List of Chapters
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 6 Freescale Semiconductor
Table of Contents
Chapter 1 General Description
1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software-Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC1 andOSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PA0-PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC0-PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD0-PD5 and PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 13 13 15 15 15 15 16 16 16 16 16 16
Chapter 2 Memory
2.1 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 17 19
Chapter 3 Central Processor Unit (CPU)
3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 24 24 24 24
Chapter 4 Interrupts
4.1 4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Non-Maskable Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 External Interrupt (IRQ or Port B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Table of Contents
4.4 4.5 4.6
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SCI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 5 Resets
5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.5 5.6 5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 29 30 30 31 31 33 33 33
Chapter 6 Low-Power Modes
6.1 6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 7 Input/Output Ports
7.1 7.2 7.3 7.4 7.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 38 38 38
Chapter 8 Capture/Compare Timer
8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.4 8.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 42 42 42 42 43 44 45 45 46 46 47 47
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Table of Contents
Chapter 9 Serial Communications Interface (SCI)
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.7.1 9.7.2 9.8 9.9 9.10 9.11 9.11.1 9.11.2 9.11.3 9.11.4 9.11.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Receiver Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Transmitter Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Data In (RDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Data Out (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 50 51 51 52 52 52 53 53 54 55 55 55 55 56 57 59
Chapter 10 Serial Peripheral Interface (SPI)
10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.5.1 10.5.2 10.5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 61 62 62 62 63 64 64 66 67
Chapter 11 Instruction Set
11.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 69 69 69 70 70 70 70 70
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 9
Table of Contents
11.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71 71 72 73 74 74 75 80
Chapter 12 Electrical Specifications
12.1 12.2 12.3 12.4 12.5 12.6 12.7 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 84 84 85 86 88 91
Chapter 13 Mechanical Specifications
13.1 13.2 13.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 14 Ordering Information
14.1 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Appendix A Self-Check Mode
A.1 A.2 A.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Self-Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Self-Check Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Appendix B M68HC05Cx Family Feature Comparisons
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 10 Freescale Semiconductor
Chapter 1 General Description
1.1 Introduction
The MC68HC05C9E HCMOS (high-density complementary metal-oxide semiconductor) microcontroller is a member of the M68HC05 Family. The MC68HC05C9E memory map consists of 15,936 bytes of user ROM and 352 bytes of RAM. The MC68HC05C9E includes a serial communications interface, a serial peripheral interface, and a 16-bit capture/compare timer.
1.2 Features
Features of the MC68HC05C9E include: * M68HC05 CPU * Mask programmable interrupt capability on port B * Software programmable external interrupt sensitivity * 15,936 bytes of read-only memory (ROM) * 352 bytes of random-access memory (RAM) * Memory mapped input/output (I/O) * 31 bidirectional I/O lines with high current sink and source on PC7 * Asynchronous serial communications interface (SCI) * Synchronous serial peripheral interface (SPI) * 16-Bit capture/compare timer * Computer operating properly (COP) watchdog timer and clock monitor * Power-saving wait and stop modes * On-chip crystal oscillator connections * Single 4.5 volts to 5.5 volts power supply requirement * ROM contents security(1) feature * Available packages: - 40-pin dual in-line (DIP) - 44-pin quad flat pack (QFP)
1.3 Mask Options
Eight mask options are available to select external interrupt capability (including an internal pullup device) on each of the port B pins.
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the ROM difficult for unauthorized users. MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 11
General Description
SELF-CHECK ROM -- 239 BYTES
USER ROM -- 15,936 BYTES PA7 USER RAM -- 352 BYTES DATA DIRECTION REGISTER A PA6 PA5 PORT A PA4 PA3 PA2 PA1 PA0
CPU CONTROL
ARITHMETIC LOGIC UNIT ACCUMULATOR
IRQ M68HC05 MCU
INDEX REGISTER RESET RESET
DATA DIRECTION REGISTER B
STACK POINTER 00000011 PROGRAM COUNTER
PB7 PB6 PB5 PORT B PB4 PB3 PB2 PB1 PB0
CONDITION CODE REGISTER 111HI NCZ CPU CLOCK OSC1 OSC2 INTERNAL OSCILLATOR DIVIDE BY TWO
DATA DIRECTION REGISTER C
PC7 PC6 PC5 PORT C PC4 PC3 PC2 PC1 PC0
COP WATCHDOG
INTERNAL CLOCK
DIVIDE BY FOUR TIMER CLOCK CAPTURE/ COMPARE TIMER BAUD RATE GENERATOR SPI SS SCK MOSI MISO VDD VSS SCI POWER TDO RDI
PD7 DATA DIRECTION REGISTER D
TCAP TCMP
PD5/SS PORT D PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI
Figure 1-1. Block Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 12 Freescale Semiconductor
Software-Programmable Options
1.4 Software-Programmable Options
The option register (OR), shown in Figure 1-2, contains the programmable bits for these options: * Map two different areas of memory between RAM and ROM, one of 48 bytes and one of 128 bytes * Edge-triggered only or edge- and level-triggered external interrupt (IRQ pin and any port B pin configured for interrupt) This register must be written to by user software during operation of the microcontroller.
Address: Read: Write: Reset: $3FDF Bit 7 RAM0 0 6 RAM1 0 5 0 0 4 0 0 3 0 0 2 0 0 1 IRQ 1 Bit 0 0 0
= Unimplemented
Figure 1-2. Option Register RAM0 -- Random-Access Memory Control Bit 0 This read/write bit selects between RAM or ROM in location $0020 to $004F. This bit can be read or written at any time. 1 = RAM selected 0 = ROM selected RAM1-- Random-Access Memory Control Bit 1 This read/write bit selects between RAM or ROM in location $0100 to $017F. This bit can be read or written at any time. 1 = RAM selected 0 = EPROM selected IRQ -- Interrupt Request Bit This bit selects between an edge-triggered only or edge- and level- triggered external interrupt. This bit is set by reset, but can be cleared by software. This bit can be written only once. 1 = Edge and level interrupt option selected 0 = Edge-only interrupt option selected
1.5 Functional Pin Descriptions
Figure 1-3 and Figure 1-4 show the pin assignments for the available packages. A functional description of the pins follows. NOTE A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 13
General Description
RESET IRQ N/C PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Figure 1-3. 40-Pin PDIP Pin Assignments
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 14 Freescale Semiconductor
Functional Pin Descriptions
RESET OSC1 OSC2 TCAP 35
44
43
42
41
40
39
38
37
36
PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
34
PD7
VDD
IRQ
PA7
N/C
N/C
N/C
33 32 31 30 29 28 27 26 25 24 23
TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3
N/C
PB4
PB5
PB6
PB7
PC7
PC6
PC5
Figure 1-4. 44-Pin QFP Pin Assignments
1.5.1 VDD and VSS
Power is supplied to the MCU using these two pins. VDD is the positive supply and VSS is ground.
1.5.2 IRQ
This interrupt pin has an option that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Chapter 4 Interrupts for more detail.
1.5.3 OSC1 andOSC2
These pins provide control input for an on-chip clock oscillator circuit. A crystal or ceramic resonator connected to these pins provides a system clock. The internal frequency is one-half the crystal frequency.
1.5.4 RESET
As an input pin, this active low RESET pin is used to reset the MCU to a known startup state by pulling RESET low. As an output pin, the RESET pin indicates that an internal MCU reset has occurred. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Chapter 5 Resets for more detail.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 15
VSS
PC4
N/C
General Description
1.5.5 TCAP
This pin controls the input capture feature for the on-chip programmable timer. The TCAP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Chapter 8 Capture/Compare Timer for more detail.
1.5.6 TCMP
The TCMP pin provides an output for the output compare feature of the on-chip programmable timer. Refer to Chapter 8 Capture/Compare Timer for more detail.
1.5.7 PA0-PA7
These eight I/O lines comprise port A. The state of each pin is software programmable and all port A pins are configured as inputs during reset. Refer to Chapter 7 Input/Output Ports for more detail.
1.5.8 PB0-PB7
These eight I/O lines comprise port B. The state of each pin is software programmable and all port B pins are configured as inputs during reset. Port B has mask option register enabled pullup devices and interrupt capability selectable for any pin. Refer to Chapter 7 Input/Output Ports for more detail.
1.5.9 PC0-PC7
These eight I/O lines comprise port C. The state of each pin is software programmable and all port C pins are configured as inputs during reset. PC7 has high current sink and source capability. Refer to Chapter 7 Input/Output Ports for more detail.
1.5.10 PD0-PD5 and PD7
These seven I/O lines comprise port D. The state of each pin is software programmable and all port D pins are configured as inputs during reset. Refer to Chapter 7 Input/Output Ports for more detail.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 16 Freescale Semiconductor
Chapter 2 Memory
2.1 Introduction
The microcontroller unit (MCU) has a 16-Kbyte memory map. The memory map consists of: * Input/output (I/O), control, and status registers * User random-access memory (RAM) * User read-only memory (ROM) * Self-check ROM * Reset and interrupt vectors See Figure 2-1 and Figure 2-2. Two control bits in the option register ($3FDF) allow the user to switch between RAM and ROM at any time in two special areas of the memory map, $0020-$004F (48 bytes) and $0100-$017F (128 bytes).
2.2 RAM
The main user RAM consists of 176 bytes at $0050-$00FF. This RAM area is always present in the memory map and includes a 64-byte stack area. The stack pointer can access 64 bytes of RAM in the range $00FF down to $00C0. NOTE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. Two additional RAM areas are available at $0020-$004F (48 bytes) and $0100-$017F (128 bytes) (see Figure 2-1 and Figure 2-2.) These may be accessed at any time by setting the RAM0 and RAM1 bits, respectively, in the option register. Refer to 1.4 Software-Programmable Options for additional information.
2.3 ROM
The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 15,872 bytes of ROM from $0100 to $3EFF, and 16 bytes of user vectors from $3FF0 to $3FFF.
2.4 ROM Security
A security feature has been incorporated into the MC68HC05C9E to help prevent external access to the contents of the ROM in any mode of operation.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 17
Memory
$0000 I/O REGISTERS 32 BYTES $001F $0020 $004F $0050 PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER PORT D DATA DIRECTION REGISTER UNUSED UNUSED SPI CONTROL REGISTER SPI STATUS REGISTER SPI DATA REGISTER SCI BAUD RATE REGISTER SCI CONTROL REGISTER 1 SCI CONTROL REGISTER 2 SCI STATUS REGISTER SCI DATA REGISTER TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT CAPTURE REGISTER (HIGH) INPUT CAPTURE REGISTER (LOW) OUTPUT COMPARE REGISTER (HIGH) OUTPUT COMPARE REGISTER (LOW) TIMER COUNTER REGISTER (HIGH) TIMER COUNTER REGISTER (LOW) ALTERNATE COUNTER REGISTER (HIGH) ALTERNATE COUNTER REGISTER (LOW) UNUSED COP RESET REGISTER COP CONTROL REGISTER UNUSED $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
USER ROM 48 BYTES RAM0 = 0
RAM 48 BYTES RAM0 = 1
RAM 176 BYTES $00BF $00C0 STACK 64 BYTES USER ROM 128 BYTES RAM1 = 0 RAM 128 BYTES RAM1 = 1
$00FF $0100
$017F $0180
USER ROM 15,744 BYTES
$3EFF $3F00 $3FF0 UNUSED (4 BYTES) SELF-CHECK ROM AND VECTORS 239 BYTES $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF
$3FDF $3FEF $3FF0
OPTION REGISTER
USER ROM VECTORS 16 BYTES $3FFF
SPI VECTOR (HIGH) SPI VECTOR (LOW) SCI VECTOR (HIGH) SCI VECTOR (LOW) TIMER VECTOR (HIGH) TIMER VECTOR (LOW) IRQ VECTOR (HIGH) IRQ VECTOR (LOW) SWI VECTOR (HIGH) SWI VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
Figure 2-1. Memory Map
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 18 Freescale Semiconductor
I/O Registers
2.5 I/O Registers
Except for the option register, all I/O, control and status registers are located within one 32-byte block in page zero of the address space ($0000-$001F). A summary of these registers is shown in Figure 2-2. More detail about the contents of these registers is given in Figure 2-3.
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F Register Name Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register Unused Unused Serial Peripheral Control Register Serial Peripheral Status Register Serial Peripheral Data Register Baud Rate Register Serial Communications Control Register 1 Serial Communications Control Register 2 Serial Communications Status Register Serial Communications Data Register Timer Control Register Timer Status Register Input Capture Register High Input Capture Register Low Output Compare Register High Output Compare Register Low Timer Register High Timer Register Low Alternate Timer Register High Alternate Timer Register Low Unused COP Reset Register COP Control Register Reserved
Figure 2-2. I/O Register Summary
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 19
Memory Addr. $0000 Register Name Port A Data Register Read: (PORTA) Write: See page 37. Reset: Port B Data Register Read: (PORTB) Write: See page 38. Reset: Port C Data Register (PORTC) Write: See page 38. Reset: Port D Data Register Read: (PORTD) Write: See page 38. Reset: Read: Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0
Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
$0001
Unaffected by reset PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
$0002
Unaffected by reset PD7 PD5 PD4 PD3 PD2 PD1 PD0
$0003
Unaffected by reset DDRA6 0 DDRB6 0 DDRC6 0 DDRA5 0 DDRB5 0 DDRC5 0 DDRC5 0 0 DDRA4 0 DDRB4 0 DDRC4 0 DDRC4 0 DDRA3 0 DDRB3 0 DDRC3 0 DDRC3 0 DDRA2 0 DDRB2 0 DDRC2 0 DDRC2 0 DDRA1 0 DDRB1 0 DDRC1 0 DDRC1 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRC0 0
$0004
Port A Data Direction Register Read: DDRA7 (DDRA) Write: See page 37. Reset: 0 Port B Data Direction Register Read: DDRB7 (DDRB) Write: See page 38. Reset: 0 Port C Data Direction Register DDRC7 (DDRC) Write: See page 38. Reset: 0 Port D Data Direction Register Read: DDRC7 (DDRD) Write: See page 38. Reset: 0 Unimplemented Unimplemented SPI Control Register Read: (SPCR) Write: See page 64. Reset: SPI Status Register Read: (SPSR) Write: See page 66. Reset: SPI Data Register (SPDR) Write: See page 67. Reset: Read: Read:
$0005
$0006
$0007 $0008 $0009
$000A
SPIE 0 SPIF 0 SPD7
SPE 0 WCOL 0 SPD6
DWOM 0 0 0 SPD5
MSTR 0 MODF 0 SPD4
CPOL 0 0 0 SPD3
CPHA 1 0 0 SPD2
SPR1 U 0 0 SPD1
SPR0 U 0 0 SPD0
$000B
$000C
Unaffected by reset = Unimplemented R = Reserved U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 1 of 3)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 20 Freescale Semiconductor
I/O Registers Addr. $000D Register Name SCI Baud Rate Register BAUD Write: See page 59. Reset: SCI Control Register 1 Read: (SCCR1) Write: See page 55. Reset: SCI Control Register 2 Read: (SCCR2) Write: See page 56. Reset: SCI Status Register Read: (SCSR) Write: See page 57. Reset: SCI Data Register (SCDR) Write: See page 55. Reset: Timer Control Register Read: (TCR) Write: See page 43. Reset: Timer Status Register Read: (TSR) Write: See page 44. Reset: Input Capture Register High Read: (ICRH) Write: See page 46. Reset: Input Capture Register Low (ICRL) Write: See page 46. Reset: Output Compare Register Read: High (OCRH) Write: See page 46. Reset: Output Compare Register Read: Low (OCRL) Write: See page 46. Reset: Timer Register High Read: (TRH) Write: See page 45. Reset: Read: Read: Read: Bit 7 6 5 SCP1 -- R8 U TIE 0 TDRE 1 SCD7 -- T8 U TCIE 0 TC 1 SDC6 0 RIE 0 RDRF 0 SCD5 0 4 SCP0 0 M U ILIE 0 IDLE 0 SCD4 -- WAKE U TE 0 OR 0 SCD3 0 RE 0 NF 0 SCD2 0 RMW 0 FE 0 SCD1 -- SCD0 0 SBK 0 3 2 SCR2 U 1 SCR1 U Bit 0 SCR0 U
$000E
$000F
$0010
$0011
Unaffected by reset ICIE 0 ICF U Bit 15 OCIE 0 OCF U Bit 14 TOIE 0 TOF U Bit 13 0 0 0 0 Bit 12 0 0 0 0 Bit 11 0 0 0 0 Bit 10 IEDG U 0 0 Bit 9 OLVL 0 0 0 Bit 8
$0012
$0013
$0014
Unaffected by reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0015
Unaffected by reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0016
Unaffected by reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0017
Unaffected by reset Bit 15 1 Bit 14 1 Bit 13 1 Bit 12 1 R Bit 11 1 = Reserved Bit 10 1 Bit 9 1 Bit 8 1
$0018
= Unimplemented
U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 2 of 3)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 21
Memory Addr. Register Name Timer Register Low (TRL) See page 45. Read: Write: Reset: Alternate Timer Register High Read: (ATRH) Write: See page 45. Reset: Alternate Timer Register Low Read: (ATRL) Write: See page 45. Reset: Unimplemented COP Reset Register Read: (COPRST) Write: See page 31. Reset: COP Control Register Read: (COPCR) Write: See page 32. Reset: Unimplemented Unimplemented Reserved R R R R R R = Reserved R R R 1 Bit 15 1 Bit 7 1 1 Bit 14 1 Bit 6 1 1 Bit 13 1 Bit 5 1 1 Bit 12 1 Bit 4 1 1 Bit 11 1 Bit 3 1 1 Bit 10 1 Bit 2 1 0 Bit 9 1 Bit 1 0 0 Bit 8 1 Bit 0 0 Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
$0019
$001A
$001B $001C
$001D
Bit 7 0 0 0
Bit 6 0 0 0
Bit 5 0 0 0
Bit 4 0 COPF U
Bit 3 0 CME 0
Bit 2 0 COPE 0
Bit 1 0 CM1 0
Bit 0 0 CM0 0
$001E $001D $001E $001F
= Unimplemented
U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 3 of 3)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 22 Freescale Semiconductor
Chapter 3 Central Processor Unit (CPU)
3.1 Introduction
This section contains information describing the basic programmer's model and the registers contained in the central processor unit (CPU).
3.2 CPU Registers
The microcontroller unit (MCU) contains five registers as shown in the programming model of Figure 3-1. The interrupt stacking order is shown in Figure 3-2.
7 A 7 X 13 PC 13 0 0 0 0 0 0 7 1 1 SP CCR H I N Z C CONDITION CODE REGISTER 0 STACK POINTER 0 PROGRAM COUNTER 0 INDEX REGISTER 0 ACCUMULATOR
Figure 3-1. Programming Model
7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1
0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL
STACK I N T E R R U P T
DECREASING MEMORY ADDRESSES
UNSTACK
Figure 3-2. Interrupt Stacking Order
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 23
Central Processor Unit (CPU)
3.2.1 Accumulator (A)
The accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
3.2.2 Index Register (X)
The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area.
3.2.3 Program Counter (PC)
The program counter is a 14-bit register that contains the address of the next byte to be fetched.
3.2.4 Stack Pointer (SP)
The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $0FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the eight most significant bits are permanently set to 00000011. These eight bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
3.2.5 Condition Code Register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained here. Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer, serial communications interface (SCI), serial peripheral interface (SPI), and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 24 Freescale Semiconductor
Chapter 4 Interrupts
4.1 Introduction
The MC68HC05C9E microcontroller unit (MCU) can be interrupted by five different sources: four maskable hardware interrupts, and one non-maskable software interrupt: * External signal on the IRQ pin or port B pins * 16-bit programmable timer * Serial communications interface (SCI) * Serial peripheral interface (SPI) * Software interrupt instruction (SWI) Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The return from interrupt (RTI) instruction causes the register contents to be recovered from the stack and normal processing to resume. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. NOTE The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If an external interrupt and a timer, SCI, or SPI interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Table 4-1 shows the relative priority of all the possible interrupt sources. Figure 4-1 shows the interrupt processing flow.
4.2 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt. It is executed regardless of the state of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 25
Interrupts
Table 4-1. Vector Addresses for Interrupts and Resets
Function Source Power-on reset Reset RESET pin COP watchdog Software interrupt (SWI) User code IRQ pin External interrupt Port B pins ICF bit Timer interrupts OCF bit TOF bit TDRE bit TCIE bit TC bit SCI interrupts RDRF bit RIE bit OR bit IDLE bit SPIF bit SPI interrupts MODF bit SPIE bit I bit 5 $3FF4-$3FF5 ILIE bit I bit 4 $3FF6-$3FF7 ICIE bit OCIE bit TOIE bit I bit 3 $3FF8-$3FF9 None I bit 2 $3FFA-$3FFB None None Same priority as instruction $3FFC-$3FFD None None 1 $3FFE-$3FFF Local Mask Global Mask Priority (1 = Highest) Vector Address
4.3 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB. When any of the port B pullups are enabled, each pin becomes an additional external interrupt source which is executed identically to the IRQ pin. Port B interrupts follow the same edge/edge-level selection as the IRQ pin. The branch instructions BIL and BIH also respond to the port B interrupts in the same way as the IRQ pin. See 7.3 Port B. Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger operation is selectable. The sensitivity is software-controlled by the IRQ bit in the option register ($3FDF). NOTE The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse can be latched and serviced as soon as the I bit is cleared.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 26 Freescale Semiconductor
Timer Interrupt
4.4 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF8 and $3FF9.
4.5 SCI Interrupt
Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7.
4.6 SPI Interrupt
Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF4 and $3FF5.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 27
Interrupts
FROM RESET
Y
I BIT IN CCR SET? N IRQ OR PORT B EXTERNAL INTERRUPT N INTERNAL TIMER INTERRUPT N INTERNAL SCI INTERRUPT N INTERNAL SPI INTERRUPT N STACK PC, X, A, CCR FETCH NEXT INSTRUCTION Y Y Y Y
CLEAR IRQ REQUEST LATCH
SET I BIT IN CC REGISTER
SWI INSTRUCTION ? N
LOAD PC FROM: Y SWI: $3FFC-$3FFD IRQ: $3FFA-$3FFB TIMER: $3FF8-$3FF9 SCI: $3FF6-$3FF7 SPI: $3FF4-$3FF5
Y
RTI INSTRUCTION ? N
RESTORE REGISTERS FROM STACK: CCR, A, X, PC
EXECUTE INSTRUCTION
Figure 4-1. Interrupt Flowchart
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 28 Freescale Semiconductor
Chapter 5 Resets
5.1 Introduction
The MC68HC05C9E microcontroller unit (MCU) can be reset four ways: * Initial power-on reset function * Active low input to the RESET pin * Computer operating properly (COP) * Clock monitor A reset immediately stops the operation of the instruction being executed, initializes some control bits, and loads the program counter with a user-defined reset vector address. Figure 5-1 is a block diagram of the reset sources.
CLOCK MONITOR
COP WATCHDOG
VDD
POWER-ON RESET STOP
RESET
R D Q RESET LATCH INTERNAL CLOCK
RST
TO CPU AND SUBSYSTEMS
Figure 5-1. Reset Sources
5.2 Power-On Reset (POR)
A power-on reset (POR) occurs when a positive transition is detected on VDD. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 internal processor clock cycle (tCYC) oscillator stabilization delay after the oscillator becomes active. The RESET pin will output a logic 0 during the 4064-cycle delay. If the RESET pin is low after the end of this 4064-cycle delay, the MCU will remain in the reset condition until RESET is driven high externally.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 29
Resets
5.3 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a period of one and one-half machine cycles (tRL). However, to differentiate between an external reset and an internal reset (generated from the COP or clock monitor), any externally driven reset must be active (logic 0) for at least eight tcyc.
V t VDDR
DD
OSC1
(2)
4064 t CYC INTERNAL (1) CLOCK INTERNAL ADDRESS BUS(1) INTERNAL DATA BUS(1)
tCYC
$3FFE NEW PCH
$3FFF NEW PCL
NEW PC DUMMY
NEW PC OP CODE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
NEW PC DUMMY
NEW PC OP CODE
PCH t RL
PCL
RESET
NOTE 4
NOTE 3
Notes: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is meant to represent only time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. RESET outputs VOL during 4064 power-on reset cycles.
Figure 5-2. Power-On Reset and RESET
5.4 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against program run-away failures. A timeout of the COP timer generates a COP reset. The COP watchdog is a software error detection system that automatically times out and resets the MCU if not cleared periodically by a program sequence. The COP is controlled with two registers, one to reset the COP timer and the other to enable and control COP and clock monitor functions. Figure 5-3 shows a block diagram of the COP.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 30 Freescale Semiconductor
Computer Operating Properly (COP) Reset
CM1 INTERNAL CPU CLOCK /4 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 CM0
16-BIT TIMER SYSTEM 213
215 217 219 /4 /2 /2 /2 /2 /2 /2 221 COP
COPRST
Figure 5-3. COP Block Diagram
5.4.1 COP Reset Register
The COP reset register (COPRST), shown in Figure 5-4, is a write-only register used to reset the COP.
Address: $001D Bit 7 Read: Write: Reset: Bit 7 0 Bit 6 0 = Unimplemented Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 6 5 4 3 2 1 Bit 0
Figure 5-4. COP Reset Register (COPRST) The sequence required to reset the COP timer is: * Write $55 to the COP reset register * Write $AA to the COP reset register Both write operations must occur in the order listed, but any number of instructions may be executed between the two write operations provided that the COP does not time out between the two writes. The elapsed time between software resets must not be greater than the COP timeout period. If the COP should time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset or reset. Reading this register does not return valid data.
5.4.2 COP Control Register
The COP control register (COPCR), shown in Figure 5-5, performs these functions: * Enables clock monitor function * Enables COP function * Selects timeout duration of COP timer And flags these conditions: * COP timeout * Clock monitor reset
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 31
Resets
Address: $001E Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 6 0 5 0 4 COPF U 3 CME 0 2 COPE 0 1 CM1 0 Bit 0 CM0 0
U = Undetermined
Figure 5-5. COP Control Register (COPCR) COPF -- Computer Operating Properly Flag Reading the COP control register clears COPF. 1 = COP or clock monitor reset has occurred. 0 = No COP or clock monitor reset has occurred. CME -- Clock Monitor Enable Bit This bit is readable any time, but may be written only once. 1 = Clock monitor enabled 0 = Clock monitor disabled COPE -- COP Enable Bit This bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by reset. 1 = COP enabled 0 = COP disabled CM1 -- COP Mode Bit 1 Used in conjunction with CM0 to establish the COP timeout period, this bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by reset. See Table 5-1 for timeout period options. CM0 -- COP Mode Bit 0 Used in conjunction with CM1 to establish the COP timeout period, this bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by reset. See Table 5-1 for timeout period options. Bits 7-5 -- Not Used These bits always read as 0. Table 5-1. COP Timeout Period
CM1 0 0 1 1 CM0 0 1 0 1 fOP/215 Divide By 1 4 16 64 Timeout Period (fOSC = 2.0 MHz) 32.77 ms 131.07 ms 524.29 ms 2.097 s Timeout Period (fOSC = 4.0 MHz) 16.38 ms 65.54 ms 262.14 ms 1.048 s
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 32 Freescale Semiconductor
COP During Wait Mode
5.5 COP During Wait Mode
The COP will continue to operate normally during wait mode. The software must pull the device out of wait mode periodically and reset the COP to prevent a system reset.
5.6 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. In the event that an inadvertent STOP instruction is executed, the COP will not provide a reset. The clock monitor function provides protection for this situation.
5.7 Clock Monitor Reset
The clock monitor circuit can provide a system reset if the clock stops for any reason, including stop mode. When the CME bit in the COP control register is set, the clock monitor detects the absence of the internal bus clock for a certain period of time. The timeout period is dependent on the processing parameters and varies from 5 s to 100 s, which implies that systems using a bus clock rate of 200 kHz or less should not use the clock monitor. If a slow or absent clock is detected, the clock monitor causes a system reset. The reset is issued to the external system via the bidirectional RESET pin for four bus cycles if the clock is slow or until the clocks recover in the case where the clocks are absent.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 33
Resets
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 34 Freescale Semiconductor
Chapter 6 Low-Power Modes
6.1 Introduction
This section describes the low-power stop and wait modes.
6.2 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest-power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. During stop mode, the TCR bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the condition code register (CCR) is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output (I/O) lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or reset. See Figure 6-1.
(1) OSC1 t RL RESET
IRQ
(2)
t LIH
IRQ
(3)
t ILCH
4064 t
CYC
INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
RESET OR INTERRUPT VECTOR FETCH
Figure 6-1. Stop Recovery Timing Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 35
Low-Power Modes
6.3 Wait Mode
The WAIT instruction places the MCU in a low-power consumption mode, but wait mode consumes more power than stop mode. All central processor unit (CPU) action is suspended, but the timer, serial communications interface (SCI), serial peripheral interface (SPI), and the oscillator remain active. Any interrupt or reset will cause the MCU to exit wait mode. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and I/O lines remain in their previous state. The timer, SCI, and SPI may be enabled to allow a periodic exit from the wait mode.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 36 Freescale Semiconductor
Chapter 7 Input/Output Ports
7.1 Introduction
This section briefly describes the 31 input/output (I/O) lines arranged as one 7-bit and three 8-bit ports. All of these port pins are programmable as either inputs or outputs under software control of the data direction registers. NOTE To avoid a glitch on the output pins, write data to the I/O port data register before writing a 1 to the corresponding data direction register.
7.2 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. The contents of the port A data register are indeterminate at initial power-up and must be initialized by user software. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. A block diagram of the port logic is shown in Figure 7-1.
DATA DIRECTION REGISTER BIT
INTERNAL HC05 CONNECTIONS
LATCHED OUTPUT DATA BIT
I/O OUTPUT PIN
INPUT REG. BIT INPUT I/O
Figure 7-1. Port A I/O Circuit
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 37
Input/Output Ports
7.3 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDR) is at $0005. The contents of the port B data register are indeterminate at initial powerup and must be initialized by user software. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port pin to output mode. Each of the port B pins has an optional external interrupt capability that can be enabled by mask option. The interrupt option also enables a pullup device when the pin is configured as an input. The edge or edge- and level-sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be taken when using port B pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a 1 to prevent an interrupt from occurring. The port B logic is shown in Figure 7-2.
7.4 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register (DDR) is at $0006. The contents of the port C data register are indeterminate at initial powerup and must be initialized by user software. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. PC7 has a high current sink and source capability. Figure 7-1 is also applicable to port C.
7.5 Port D
Port D is a 7-bit bidirectional port. Four of its pins are shared with the SPI subsystem and two more are shared with the SCI subsystem. The port D data register is at $0003 and the data direction register is at $0007. The contents of the port D data register are indeterminate at initial powerup and must be initialized by user software. During reset all seven bits become valid input ports because the DDR bits are cleared and the special function output drivers associated with the SCI and SPI subsystems are disabled, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 38 Freescale Semiconductor
Port D
VDD DISABLED PORT B EXTERNAL INTERRUPT MASK OPTION ENABLED READ $0005 WRITE $0005 INTERNAL DATA BUS RESET
VDD
DATA DIRECTION REGISTER B BIT DDRB7 PORT B DATA REGISTER BIT PB7
WRITE $0001
PBX
READ $0001
SOFTWARE CONTROLLED OPTION
EDGE ONLY
EDGE AND LEVEL
VDD D FROM OTHER PORT B PINS Q EXTERNAL INTERRUPT REQUEST I BIT FROM CCR IRQ
C
R
Q
RESET EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-2. Port B I/O Logic
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 39
Input/Output Ports
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 40 Freescale Semiconductor
Chapter 8 Capture/Compare Timer
8.1 Introduction
This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 shows the structure of the capture/compare subsystem.
INTERNAL BUS INTERNAL PROCESSOR CLOCK /4
HIGH LOW BYTE BYTE
8-BIT BUFFER HIGH LOW BYTE BYTE INPUT $14 CAPTURE $15 REGISTER
$16 $17
OUTPUT COMPARE REGISTER
HIGH BYTE
LOW BYTE
16-BIT FREE $18 RUNNING $19 COUNTER COUNTER $1A ALTERNATE $1B REGISTER
OUTPUT COMPARE CIRCUIT
OVERFLOW DETECT CIRCUIT
EDGE DETECT CIRCUIT DQ CLK C RESET
TIMER STATUS ICF OCF TOF $13 REG.
OUTPUT LEVEL REG.
TIMER ICIE OCIE TOIE IEDG OLVL CONTROL REG. $12 INTERRUPT CIRCUIT
OUTPUT LEVEL (TCMP)
EDGE INPUT (TCAP)
Figure 8-1. Capture/Compare Timer Block Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 41
Capture/Compare Timer
8.2 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter. The counter provides the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affecting the counter sequence. Because of the 16-bit timer architecture, the input/output (I/O) registers for the input capture and output compare functions are pairs of 8-bit registers. Because the counter is 16 bits long and preceded by a fixed divide-by-4 prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4-MHz crystal is 2 s.
8.2.1 Input Capture
The input capture function is a means to record the time at which an external event occurs. When the input capture circuitry detects an active edge on the TCAP pin, it latches the contents of the timer registers into the input capture registers. The polarity of the active edge is programmable. Latching values into the input capture registers at successive edges of the same polarity measures the period of the input signal on the TCAP pin. Latching values into the input capture registers at successive edges of opposite polarity measures the pulse width of the signal.
8.2.2 Output Compare
The output compare function is a means of generating an output signal when the 16-bit counter reaches a selected value. Software writes the selected value into the output compare registers. On every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers. When a match occurs, the timer transfers the programmable output level bit (OLVL) from the timer control register to the TCMP pin. The programmer can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the TCMP pin.
8.3 Timer I/O Registers
These I/O registers control and monitor timer operation: * Timer control register (TCR) * Timer status register (TSR) * Timer registers (TRH and TRL) * Alternate timer registers (ATRH and ATRL) * Input capture registers (ICRH and ICRL) * Output compare registers (OCRH and OCRL)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 42 Freescale Semiconductor
Timer I/O Registers
8.3.1 Timer Control Register
The timer control register (TCR), shown in Figure 8-2, performs these functions: * Enables input capture interrupts * Enables output compare interrupts * Enables timer overflow interrupts * Controls the active edge polarity of the TCAP signal * Controls the active level of the TCMP output
Address: Read: Write: Reset: $0012 Bit 7 ICIE 0 6 OCIE 0 5 TOIE 0 4 0 0 3 0 0 2 0 0 1 IEDG U Bit 0 OLVL 0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCAP pin. Reset clears the ICIE bit. 1 = Input capture interrupts enabled 0 = Input capture interrupts disabled OCIE -- Output Compare Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCMP pin. Reset clears the OCIE bit. 1 = Output compare interrupts enabled 0 = Output compare interrupts disabled TOIE -- Timer Overflow Interrupt Enable Bit This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled IEDG -- Input Edge Bit The state of this read/write bit determines whether a positive or negative transition on the TCAP pin triggers a transfer of the contents of the timer register to the input capture register. Resets have no effect on the IEDG bit. 1 = Positive edge (low to high transition) triggers input capture. 0 = Negative edge (high to low transition) triggers input capture. OLVL -- Output Level Bit The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when a successful output compare occurs. Reset clears the OLVL bit. 1 = TCMP goes high on output compare. 0 = TCMP goes low on output compare.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 43
Capture/Compare Timer
8.3.2 Timer Status Register
The timer status register (TSR), shown in Figure 8-3, contains flags to signal these conditions: * An active signal on the TCAP pin, transferring the contents of the timer registers to the input capture registers * A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the TCMP pin * A timer roll over from $FFFF to $0000
Address: Read: Write: Reset: U U U 0 U = Unaffected 0 0 0 0 = Unimplemented $0013 Bit 7 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0
Figure 8-3. Timer Status Register (TSR) ICF -- Input Capture Flag The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin. Clear the ICF bit by reading the timer status register with ICF set and then reading the low byte ($0015) of the input capture registers. Resets have no effect on ICF. OCF -- Output Compare Flag The OCF bit is set automatically when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with OCF set and then reading the low byte ($0017) of the output compare registers. Resets have no effect on OCF. TOF -- Timer Overflow Flag The TOF bit is set automatically when the 16-bit counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with TOF set, and then reading the low byte ($0019) of the timer registers. Resets have no effect on TOF.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 44 Freescale Semiconductor
Timer I/O Registers
8.3.3 Timer Registers
The timer registers (TRH and TRL), shown in Figure 8-4, contain the current high and low bytes of the 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer registers has no effect.
Address: Read: Write Reset: Address: Read: Write: Reset: 1 1 1 1 1 1 0 0 = Unimplemented 1 $0019 -- TRL Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 1 1 1 1 1 1 1 $0018 -- TRH Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Figure 8-4. Timer Registers (TRH and TRL)
8.3.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL), shown in Figure 8-5, contain the current high and low bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL is read. Reading ATRL has no effect on the timer overflow flag (TOF). Writing to the alternate timer registers has no effect.
Address: Read: Write: Reset: Address: Read: Write: Reset: 1 1 1 1 1 1 0 0 = Unimplemented 1 $001B -- ATRL Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 1 1 1 1 1 1 1 $001A -- ATRH Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Figure 8-5. Alternate Timer Registers (ATRH and ATRL) NOTE To prevent interrupts from occurring between readings of ATRH and ATRL, set the interrupt flag in the condition code register before reading ATRH, and clear the flag after reading ATRL.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 45
Capture/Compare Timer
8.3.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the input capture registers. Reading ICRH before reading ICRL inhibits further capture until ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to the input capture registers has no effect.
Address: Read: Write: Reset: Address: Read: Write: Reset: = Unimplemented Unaffected by reset $0015 -- ICRL Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Unaffected by reset $0014 -- ICRH Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Figure 8-6. Input Capture Registers (ICRH and ICRL) NOTE To prevent interrupts from occurring between readings of ICRH and ICRL, set the interrupt flag in the condition code register before reading ICRH, and clear the flag after reading ICRL.
8.3.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output compare registers, the planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF).
Address: Write: Read: Reset: Address: Write: Read: Reset: $0017 -- OCRL Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 $0016 -- OCRH Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Unaffected by reset
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 46 Freescale Semiconductor
Timer During Wait Mode
To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. Disable interrupts by setting the I bit in the CCR. 2. Write to OCRH. Compares are now inhibited until OCRL is written. 3. Clear bit OCF by reading timer status register (TSR). 4. Enable the output compare function by writing to OCRL. 5. Enable interrupts by clearing the I bit in the CCR.
8.4 Timer During Wait Mode
The central processor unit (CPU) clock halts during wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode.
8.5 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt. If STOP is exited by reset, the counters are forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any timer flags or wake up the microcontroller unit (MCU). But if an interrupt is used to exit stop mode, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 47
Capture/Compare Timer
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 48 Freescale Semiconductor
Chapter 9 Serial Communications Interface (SCI)
9.1 Introduction
This section describes the on-chip asynchronous serial communications interface (SCI). The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the microcontroller unit (MCU) and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator.
9.2 Features
Features of the SCI include: * Standard mark/space non-return-to-zero format * Full-duplex operation * 32 programmable baud rates * Programmable 8-bit or 9-bit character length * Separately enabled transmitter and receiver * Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup * Interrupt-driven operation capability with five interrupt flags: - Transmitter data register empty - Transmission complete - Transmission data register full - Receiver overrun - Idle receiver input * Receiver framing error detection * 1/16 bit-time noise detection NOTE The serial communications data register (SCI SCDR) is controlled by the internal R/W signal. It is the transmit data register when written to and the receive data register when read.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 49
Serial Communications Interface (SCI)
INTERNAL BUS SCI INTERRUPT + $0011 TRANSMIT DATA REGISTER $0011 RECEIVE DATA REGISTER
& TDO PIN TRANSMIT DATA SHIFT REGISTER
&
&
&
+ SCSR $0010 1 FE
$000F SCCR2 TIE TCIE RIE ILIE TE RE SBK RWU
7 6 5 4 3 2 1 0
RECEIVE DATA SHIFT REGISTER
RDI PIN
7 TRDE
6 TC
5 RDRF
4 IDLE
3 OR
2 NF
WAKEUP UNIT
TE
SBK
7 FLAG CONTROL RECEIVER CONTROL RECEIVER CLOCK
TRANSMITTER CONTROL
7 R8
6 T8
5
4 M
3 WAKE
2
1
0
SCCR1 $000E
Figure 9-1. Serial Communications Interface Block Diagram
9.3 SCI Receiver Features
Features of the SCI receiver include: * Receiver wakeup function (idle line or address bit) * Idle line detection * Framing error detection * Noise detection * Overrun detection * Receiver data register full flag
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 50 Freescale Semiconductor
SCI Transmitter Features
9.4 SCI Transmitter Features
Features of the SCI transmitter include: * Transmit data register empty flag * Transmit complete flag * Send break
9.5 Functional Description
A block diagram of the SCI is shown in Figure 9-1. Option bits in serial control register1 (SCCR1) select the wakeup method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides control bits that individually enable the transmitter and receiver, enable system interrupts, and provide the wakeup enable bit (RWU) and the send break code bit (SBK). Control bits in the baud rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and receiver. Data transmission is initiated by writing to the serial communications data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The transfer of data to the transmit data shift register is synchronized with the bit rate clock (see Figure 9-2). All data is transmitted least significant bit first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble, or break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If the transmitter is disabled, and the data, preamble, or break (in the transmit data shift register) has been sent, the TC bit will be set also. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the TDO pin. When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR may be set if data reception errors occurred. An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) in SCSR is set. This allows a receiver that is not in the wakeup mode to detect the end of a message, or the preamble of a new message, or to re-synchronize with the transmitter. A valid character must be received before the idle line condition or the IDLE bit will not be set and idle line interrupt will not be generated.
SCP0-SCP1 OSC FREQ (fOSC) /2 BUS FREQ (fOP) SCI PRESCALER SELECT CONTROL N
SCR0-SCR2 SCI RATE SELECT CONTROL M SCI RECEIVE CLOCK (RT) / 16 SCI TRANS CLOCK (TX)
Figure 9-2. Rate Generator Division
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 51
Serial Communications Interface (SCI)
9.6 Data Format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The non-return-to-zero (NRZ) data format shown in Figure 9-3 is used and must meet these criteria: * The idle line is brought to a logic 1 state prior to transmission/ reception of a character. * A start bit (logic 0) is used to indicate the start of a frame. * The data is transmitted and received least significant bit first. * A stop bit (logic 1) is used to indicate the end of a frame. A frame consists of a start bit, a character of eight or nine data bits, and a stop bit. * A break is defined as the transmission or reception of a low (logic 0) for at least one complete frame time.
CONTROL BIT M SELECTS 8- OR 9-BIT DATA IDLE LINE 0 START 1 2 3 4 5 6 7 8 0 STOP START
Figure 9-3. Data Format
9.7 Receiver Wakeup Operation
The receiver logic hardware also supports a receiver wakeup function which is intended for systems having more than one receiver. With this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. The wakeup function allows receivers not addressed to remain in a dormant state for the remainder of the unwanted message. This eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves system performance. The receiver is placed in wakeup mode by setting the receiver wakeup bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set). NOTE The idle line detect function is inhibited while the RWU bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do so. Normally, RWU is set by software and is cleared automatically in hardware by one of these methods: idle line wakeup or address mark wakeup.
9.7.1 Idle Line Wakeup
In idle line wakeup mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for 10 (or 11) full bit times. Systems using this type of wakeup must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 52 Freescale Semiconductor
Receive Data In (RDI)
9.7.2 Address Mark Wakeup
In address mark wakeup, the most significant bit (MSB) in a character is used to indicate whether it is an address (logic 1) or data (logic 0) character. Sleeping receivers will wake up whenever an address character is received. Systems using this method for wakeup would set the MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wakeup method.
9.8 Receive Data In (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the RT rate in Figure 9-4 and as the receiver clock in Figure 9-6.
16X INTERNAL SAMPLING CLOCK RT CLOCK EDGES FOR ALL THREE EXAMPLES IDLE RDI 1 1 1 1 1 1 1 1 0 START RDI 1 1 1 1 NOISE RDI 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 START 0 1 0 0 0 NOISE 0 1RT START 2RT 3RT 4RT 5RT 6RT 7RT
Figure 9-4. SCI Examples of Start Bit Sampling Techniques The receiver clock generator is controlled by the baud rate register; however, the SCI is synchronized by the start bit, independent of the transmitter. Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three times at RT intervals 8RT, 9RT, and 10RT (1RT is the position where the bit is expected to start), as shown in Figure 9-5. The value of the bit is determined by voting logic which takes the value of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree.
PREVIOUS BIT RDI 16RT 1RT 8RT 9RT 10RT 16RT 1RT SAMPLES NEXT BIT
Figure 9-5. SCI Sampling Technique Used on All Bits
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 53
Serial Communications Interface (SCI)
9.9 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start edge verification samples in Figure 9-4). If at least two of these three verification samples detect a logic 0, a valid start bit has been detected; otherwise, the line is assumed to be idle. A noise flag is set if all three verification samples do not detect a logic 0. Thus, a valid start bit could be assumed with a set noise flag present. If a framing error has occurred without detection of a break (10 0s for 8-bit format or 11 0s for 9-bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. The last bit received in the data shift register is inverted to a logic 1, and the three logic 1 start qualifiers (shown in Figure 9-4) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see Figure 9-6); therefore, the start bit will be accepted no sooner than it is anticipated.
DATA RDI
EXPECTED STOP
ARTIFICIAL EDGE START BIT
DATA
DATA SAMPLES
a) Case 1: Receive Line Low During Artificial Edge
DATA RDI
EXPECTED STOP
START EDGE START BIT
DATA
DATA SAMPLES
b) Case 2: Receive Line High During Expected Start Edge
Figure 9-6. SCI Artificial Start Following a Frame Error If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $003B) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic 1 before the start bit can be recognized (see Figure 9-7).
EXPECTED STOP BREAK RDI
DETECTED AS VALID START EDGE START BIT START START EDGE QUALIFIERS VERIFICATION SAMPLES
DATA SAMPLES
Figure 9-7. SCI Start Bit Following a Break
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 54 Freescale Semiconductor
Transmit Data Out (TDO)
9.10 Transmit Data Out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the output line. Data format is as discussed in 9.6 Data Format and shown in Figure 9-3. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock.
9.11 SCI I/O Registers
These I/O registers control and monitor SCI operation: * SCI data register (SCDR) * SCI control register 1 (SCCR1) * SCI control register 2 (SCCR2) * SCI status register (SCSR)
9.11.1 SCI Data Register
The SCI data register (SCDR), shown in Figure 9-8, is the buffer for characters received and for characters transmitted.
Address: $0011 Bit 7 Read: SCD7 Write: Reset: 6 SDC6 5 SCD5 4 SCD4 3 SCD3 2 SCD2 1 SCD1 Bit 0 SCD0
Unaffected by reset
Figure 9-8. SCI Data Register (SCDR)
9.11.2 SCI Control Register 1
The SCI control register 1 (SCCR1), shown in Figure 9-9, has these functions: * Stores ninth SCI data bit received and ninth SCI data bit transmitted * Controls SCI character length * Controls SCI wakeup method
Address: $000E Bit 7 Read: R8 Write: Reset: U 6 T8 U 0 = Unimplemented 5 4 M 3 WAKE 0 0 0 2 1 Bit 0
U U U = Undetermined
Figure 9-9. SCI Control Register 1 (SCCR1) R8 -- Bit 8 (Received) When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives the ninth bit at the same time that the SCDR receives the other eight bits. Resets have no effect on the R8 bit. T8 -- Bit 8 (Transmitted) When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit register. Resets have no effect on the T8 bit.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 55
Serial Communications Interface (SCI)
M -- Character Length Bit This read/write bit determines whether SCI characters are 8 bits long or 9 bits long. The ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. Resets have no effect on the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE -- Wakeup Method Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit (MSB) position of a received character or an idle condition on the PD0/RDI pin. Resets have no effect on the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup
9.11.3 SCI Control Register 2
SCI control register 2 (SCCR2), shown in Figure 9-10, has these functions: * Enables the SCI receiver and SCI receiver interrupts * Enables the SCI transmitter and SCI transmitter interrupts * Enables SCI receiver idle interrupts * Enables SCI transmission complete interrupts * Enables SCI wakeup * Transmits SCI break characters
Address: $000F Bit 7 Read: Write: Reset: TIE 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0
Figure 9-10. SCI Control Register 2 (SCCR2) TIE -- Transmit Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TDRE flag becomes set. Resets clear the TIE bit. 1 = TDRE interrupt requests enabled 0 = TDRE interrupt requests disabled TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TC flag becomes set. Resets clear the TCIE bit. 1 = TC interrupt requests enabled 0 = TC interrupt requests disabled RIE -- Receiver Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the RDRF flag or the OR flag becomes set. Resets clear the RIE bit. 1 = RDRF interrupt requests enabled 0 = RDRF interrupt requests disabled
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 56 Freescale Semiconductor
SCI I/O Registers
ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Resets clear the ILIE bit. 1 = IDLE interrupt requests enabled 0 = IDLE interrupt requests disabled TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PD1/TDO pin. Resets clear the TE bit. 1 = Transmission enabled 0 = Transmission disabled RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. Resets clear the RE bit. 1 = Receiver enabled 0 = Receiver disabled RWU -- Receiver Wakeup Enable Bit This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines whether an idle input or an address mark brings the receiver out of standby state. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send Break Bit Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops the break codes and transmits a logic 1 as a start bit. Reset clears the SBK bit. 1 = Break codes being transmitted 0 = No break codes being transmitted
9.11.4 SCI Status Register
The SCI status register (SCSR), shown in Figure 9-11, contains flags to signal these conditions: * Transfer of SCDR data to transmit shift register complete * Transmission complete * Transfer of receive shift register data SCDR complete * Receiver input idle * Noisy data * Framing error
Address: Read: Write: Reset: 1 1 = Unimplemented 0 0 0 0 0 -- $0010 Bit 7 TDRE 6 TC 5 RDRF 4 IDLE 3 OR 2 NF 1 FE Bit 0
Figure 9-11. SCI Status Register (SCSR)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 57
Serial Communications Interface (SCI)
TDRE -- Transmit Data Register Empty Flag This clearable, read-only flag is set when the data in the SCDR transfers to the transmit shift register. TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading the SCSR with TDRE set and then writing to the SCDR. Reset sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to avoid an instant interrupt request when turning the transmitter on. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission Complete Flag This clearable, read-only flag is set when the TDRE bit is set, and no data, preamble, or break character is being transmitted. TDRE generates an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC bit by reading the SCSR with TC set, and then writing to the SCDR. Reset sets the TC bit. Software must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning the transmitter on. 1 = No transmission in progress 0 = Transmission in progress RDRF -- Receive Data Register Full Flag This clearable, read-only flag is set when the data in the receive shift register transfers to the SCI data register. RDRF generates an interrupt request if the RIE bit in the SCCR2 is also set. Clear the RDRF bit by reading the SCSR with RDRF set and then reading the SCDR. 1 = Received data available in SCDR 0 = Received data not available in SCDR IDLE -- Receiver Idle Flag This clearable, read-only flag is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an interrupt request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by reading the SCSR with IDLE set and then reading the SCDR. 1 = Receiver input idle 0 = Receiver input not idle OR -- Receiver Overrun Flag This clearable, read-only flag is set if the SCDR is not read before the receive shift register receives the next word. OR generates an interrupt request if the RIE bit in the SCCR2 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading the SCSR with OR set and then reading the SCDR. 1 = Receive shift register full and RDRF = 1 0 = No receiver overrun NF -- Receiver Noise Flag This clearable, read-only flag is set when noise is detected in data received in the SCI data register. Clear the NF bit by reading the SCSR and then reading the SCDR. 1 = Noise detected in SCDR 0 = No noise detected in SCDR FE -- Receiver Framing Error Flag This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. If the received word causes both a framing error and an overrun error, the OR flag is set and the FE flag is not set. Clear the FE bit by reading the SCSR and then reading the SCDR. 1 = Framing error 0 = No framing error
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 58 Freescale Semiconductor
SCI I/O Registers
9.11.5 Baud Rate Register
The baud rate register (BAUD), shown in Figure 9-12, selects the baud rate for both the receiver and the transmitter.
Address: $000D Bit 7 Read: Write: Reset: -- -- = Unimplemented 6 5 SCP1 0 4 SCP0 0 U = Unaffected -- 3 2 SCR2 U 1 SCR1 U Bit 0 SCR0 U
Figure 9-12. Baud Rate Register (BAUD) SCP1 -- SCP0-SCI Prescaler Select Bits These read/write bits control prescaling of the baud rate generator clock, as shown in Table 9-1. Reset clears both SCP1 and SCP0. Table 9-1. Baud Rate Generator Clock Prescaling
SCP1 and SCP0 00 01 10 11 Baud Rate Generator Clock Internal clock / 1 Internal clock / 3 Internal clock / 4 Internal clock / 13
SCR2 -- SCR0-SCI Baud Rate Select Bits These read/write bits select the SCI baud rate, as shown in Table 9-2. Resets have no effect on the SCR2-SCR0 bits. Table 9-2. Baud Rate Selection
SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 SCI Baud Rate (Baud) Prescaled clock / 1 Prescaled clock / 2 Prescaled clock / 4 Prescaled clock / 8 Prescaled clock / 16 Prescaled clock / 32 Prescaled clock / 64 Prescaled clock / 128
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 59
Serial Communications Interface (SCI)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 60 Freescale Semiconductor
Chapter 10 Serial Peripheral Interface (SPI)
10.1 Introduction
The serial peripheral interface (SPI) is an interface built into the device which allows several M68HC05 microcontroller units (MCU), or M68HC05 MCU plus peripheral devices, to be interconnected within a single printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. An SPI system may be configured in one containing one master MCU and several slave MCUs or in a system in which an MCU is capable of being a master or a slave.
10.2 Features
SPI features include: * Full-duplex, 4-wire synchronous transfers * Master or slave operation * Bus frequency divided by 2 (maximum) master bit frequency * Bus frequency (maximum) slave bit frequency * Four programmable master bit rates * Programmable clock polarity and phase * End-of-transmission interrupt flag * Write collision flag protection * Master-master mode fault protection capability
10.3 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described here. Each signal function is described for both the master and slave modes. NOTE Any SPI output line has to have its corresponding data direction register bit set. If this bit is clear, the line is disconnected from the SPI logic and becomes a general-purpose input line. When the SPI is enabled, any SPI input line is forced to act as an input regardless of what is in the corresponding data direction register bit.
10.3.1 Master In/Slave Out (MISO)
The MISO line is configured as an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 61
Serial Peripheral Interface (SPI)
SS
SCK
CPOL = 0 CPHA = 0
SCK
CPOL = 0 CPHA = 1
SCK
CPOL = 1 CPHA = 0
SCK
CPOL = 1 CPHA = 1
MISO/MOSI MSB 6 5 4 3 2 1 0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.3.2 Master Out/Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data in one direction with the most significant bit sent first.
10.3.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. As shown in Figure 10-1, four possible timing relationships may be chosen by using control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line a half cycle before the clock edge (SCK), in order for the slave device to latch the data. Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
10.3.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions and must stay low for the duration of the transaction.The SS line on the master must be tied high. In master mode, if the SS pin is pulled low during a transmission, a mode fault error flag (MODF) is set in the SPSR. In master mode the SS pin can be selected as a general-purpose output by writing a 1 in bit 5 of the port D data direction register, thus disabling the mode fault circuit.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 62 Freescale Semiconductor
Functional Description
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device transmits data to a slave via the MOSI line, the slave device responds by sending data to the master device via the master's MISO line. This implies full duplex transmission with both data out and data in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that the input/output (I/O) operation has been completed.
S M SPI SHIFT REGISTER 76543210 M S PD2/ MISO PD3/ MOSI
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL CLOCK (XTAL /2)
SPIE SPE MSTR SPI CONTROL
SPIF WCOL MODF
/2
DIVIDER / 4 / 16
SHIFT CLOCK SPI INTERRUPT REQUEST PD5/ SS SPI CLOCK SLAVE SPI CLOCK MASTER
/ 32
SELECT
SPI CLOCK (MASTER)
CLOCK LOGIC
PD4/ SCK
SPR1
SPR0 7 SPIE SPIF BIT 7
MSTR 6 SPE WCOL BIT 6
CPHA 5 DWOM 0 BIT 5
CPOL 4 MSTR MODF BIT 4 3 CPOL 0 BIT 3
SPI CONTROL REGISTER (SPCR) SPI STATUS REGISTER (SPSR) SPI DATA REGISTER (SPDR)
2 CPHA 0 BIT 2
1 SPR1 0 BIT 1
0 SPR2 0 BIT 0
$000A $000B $000C
Figure 10-2. Serial Peripheral Interface Block Diagram The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR is set.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 63
Serial Peripheral Interface (SPI)
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again. In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave's MISO line. Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
PD3/MOSI SPI SHIFT REGISTER 76543210 PD2/MISO PD5/SS I/O PORT SPDR ($000C) PD4/SCK MASTER MCU SLAVE MCU SPDR ($000C) SPI SHIFT REGISTER 76543210
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.5 SPI Registers
This subsection describes the three registers in the SPI which provide control, status, and data storage functions. These registers are: * Serial peripheral control register (SPCR) * Serial peripheral status register (SPSR) * Serial peripheral data I/O register (SPDR)
10.5.1 Serial Peripheral Control Register
The SPI control register (SPCR), shown in Figure 10-4, controls these functions: * Enables SPI interrupts * Enables the SPI system * Selects between standard CMOS or open drain outputs for port D * Selects between master mode and slave mode * Controls the clock/data relationship between master and slave * Determines the idle level of the clock pin
Address: Read: Write: Reset: $000A Bit 7 SPIE 6 SPE 5 DWOM 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SPR1 U Bit 0 SPR0 U
0 0 U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 64 Freescale Semiconductor
SPI Registers
SPIE -- Serial Peripheral Interrupt Enable Bit This read/write bit enables SPI interrupts. Reset clears the SPIE bit. 1 = SPI interrupts enabled 0 = SPI interrupts disabled SPE -- Serial Peripheral System Enable Bit This read/write bit enables the SPI. Reset clears the SPE bit. 1 = SPI system enabled 0 = SPI system disabled DWOM -- Port D Wire-OR Mode Option Bit This read/write bit disables the high side driver transistors on port D outputs so that port D outputs become open-drain drivers. DWOM affects all seven port D pins together. 1 = Port D outputs act as open-drain outputs. 0 = Port D outputs are normal CMOS outputs. MSTR -- Master Mode Select Bit This read/write bit selects master mode operation or slave mode operation. Reset clears the MSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. See Figure 10-1. CPHA -- Clock Phase Bit The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA = 0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA=1, the SS pin may be thought of as a simple output enable control. See Figure 10-1. SPR1 and SPR0 -- SPI Clock Rate Select Bits These read/write bits select one of four master mode serial clock rates, as shown in Table 10-1. They have no effect in slave mode. Table 10-1. SPI Clock Rate Selection
SPR1 and SPR0 00 01 10 11 SPI Clock Rate Internal clock / 2 Internal clock / 4 Internal clock / 16 Internal clock / 32
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 65
Serial Peripheral Interface (SPI)
10.5.2 Serial Peripheral Status Register
The SPI status register (SPSR), shown in Figure 10-5, contains flags to signal these conditions: * SPI transmission complete * Write collision * Mode fault
Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented $000B Bit 7 SPIF 6 WCOL 5 0 4 MODF 3 0 2 0 1 0 Bit 0 0
Figure 10-5. SPI Status Register SPIF -- SPI Transfer Complete Flag The serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an access of the SPDR. Following the initial transfer, unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited. WCOL -- Write Collision Bit The write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. If CPHA is 0, a transfer is said to begin when SS goes low and the transfer ends when SS goes high after eight clock cycles on SCK. When CPHA is 1, a transfer is said to begin the first time SCK becomes active while SS is low and the transfer ends when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access to SPDR. MODF -- Mode Fault Flag The mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. The MODF bit is normally clear, and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects the internal serial peripheral interface system in these ways: 1. An SPI interrupt is generated if SPIE = 1. 2. The SPE bit is cleared. This disables the SPI. 3. The MSTR bit is cleared, thus forcing the device into the slave mode. Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to the SPCR. Control bits SPE and MSTR may be restored by user software to their original state during this clearing sequence or after the MODF bit has been cleared. It is also necessary to restore DDRD after a mode fault. Bits 5 and 3-0 -- Not Implemented These bits always read 0.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 66 Freescale Semiconductor
SPI Registers
10.5.3 Serial Peripheral Data I/O Register
The serial peripheral data I/O register (SPDR), shown in Figure 10-6, is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte and this will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission.
Address: Read: Write: Reset: $000C Bit 7 SPD7 6 SPD6 5 SPD5 4 SPD4 3 SPD3 2 SPD2 1 SPD1 Bit 0 SPD0
Unaffected by reset
Figure 10-6. SPI Data Register (SPDR)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 67
Serial Peripheral Interface (SPI)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 68 Freescale Semiconductor
Chapter 11 Instruction Set
The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS (complementary metal-oxide semiconductor) Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
11.1 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * Inherent * Immediate * Direct * Extended * Indexed, no offset * Indexed, 8-bit offset * Indexed, 16-bit offset * Relative
11.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
11.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
11.1.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 69
Instruction Set
11.1.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
11.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (RAM) or input/output (I/O) location.
11.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
11.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing.
11.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 70 Freescale Semiconductor
Instruction Types
11.2 Instruction Types
The MCU instructions fall into these five categories: * Register/memory instructions * Read-modify-write instructions * Jump/branch instructions * Bit manipulation instructions * Control instructions
11.2.1 Register/Memory Instructions
These instructions operate on central processor unit (CPU) registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions
Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 71
Instruction Set
11.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE Do not use read-modify-write operations on write-only registers. Table 11-2. Read-Modify-Write Instructions
Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 72 Freescale Semiconductor
Instruction Types
11.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 11-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 73
Instruction Set
11.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions
Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Mnemonic BCLR BRCLR BRSET BSET
11.2.5 Control Instructions
These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 74 Freescale Semiconductor
Instruction Set Summary
11.3 Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 1 of 6)
Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
2 A9 ii B9 dd 3 C9 hh ll 4 D9 ee ff 5 4 E9 ff 3 F9 2 AB ii BB dd 3 CB hh ll 4 DB ee ff 5 4 EB ff 3 FB 2 A4 ii B4 dd 3 C4 hh ll 4 D4 ee ff 5 4 E4 ff 3 F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 2F 2E dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ---------- ---------- ----------
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 75
Cycles
Effect on CCR
Operand
Address Mode
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 2 of 6)
Opcode Source Form
BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Description
H I NZC
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
2 A5 ii B5 dd 3 C5 hh ll 4 D5 ee ff 5 4 E5 ff 3 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
----------
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
--------
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
----------
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
--------
BSET n opr
Set Bit n
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 76 Freescale Semiconductor
Cycles
6 2 2
Effect on CCR
Operand
Address Mode
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 3 of 6)
Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
Compare Accumulator with Memory Byte
(A) - (M)
----
2 A1 ii B1 dd 3 C1 hh ll 4 D1 ee ff 5 4 E1 ff 3 F1 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
ff
Compare Index Register with Memory Byte
(X) - (M)
----
2 A3 ii B3 dd 3 C3 hh ll 4 D3 ee ff 5 4 E3 ff 3 F3 3A 4A 5A 6A 7A dd 5 3 3 6 5
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
2 A8 ii B8 dd 3 C8 hh ll 4 D8 ee ff 5 4 E8 ff 3 F8 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 BD dd 5 CD hh ll 6 DD ee ff 7 6 ED ff 5 FD
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
----------
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 77
Cycles
5 3 3 6 5
Effect on CCR
Operand
Address Mode
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 4 of 6)
Opcode Source Form
LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Load Accumulator with Memory Byte
A (M)
----
--
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH
2 A6 ii B6 dd 3 C6 hh ll 4 D6 ee ff 5 4 E6 ff 3 F6 2 AE ii BE dd 3 CE hh ll 4 DE ee ff 5 4 EE ff 3 FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 36 46 56 66 76 9C ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 1 1 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
ff
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
Rotate Byte Left through Carry Bit
C b7 b0
----
ff dd
Rotate Byte Right through Carry Bit
b7 b0
C
----
ff
Reset Stack Pointer
SP $00FF
----------
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 78 Freescale Semiconductor
Cycles
Effect on CCR
Operand
Address Mode
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 5 of 6)
Opcode Source Form Operation Description
SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ----------
H I NZC
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
2 A2 ii B2 dd 3 C2 hh ll 4 D2 ee ff 5 4 E2 ff 3 F2 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
Store Accumulator in Memory
M (A)
----
--
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
Subtract Memory Byte from Accumulator
A (A) - (M)
----
2 A0 ii B0 dd 3 C0 hh ll 4 D0 ee ff 5 4 E0 ff 3 F0
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
TAX TST opr TSTA TSTX TST opr,X TST ,X
Transfer Accumulator to Index Register
INH DIR INH INH IX1 IX
97 3D 4D 5D 6D 7D dd
Test Memory Byte for Negative or Zero
(M) - $00
----
--
ff
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 79
Cycles
9 6 1 0 2 4 3 3 5 4
Effect on CCR
Operand
Address Mode
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 6 of 6)
Opcode Source Form
TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Operation
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts
Description
A (X)
H I NZC
---------- -- 0 ------ opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
INH INH
9F 8F
Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
11.4 Opcode Map
See Table 11-7.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 80 Freescale Semiconductor
Cycles
2 2
Effect on CCR
Operand
Address Mode
Freescale Semiconductor MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 81
Table 11-7. Opcode Map
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2
DIR 3
Read-Modify-Write INH INH IX1 4 5 6
IX 7
Control INH INH 8
9 RTI INH 6 RTS INH
IMM A
2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2
DIR B
Register/Memory EXT IX2 C
4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3
IX1 E
4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
IX F
3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB
0
1
9
D
5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2
0 1 2 3 4 5 6 7 8 9 A B C D E F
5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1
2 2 2
10 SWI INH
2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2
2 STOP INH 2 2 WAIT TXA INH 1 INH
6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB
3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3
0 1 2 3 4 5 6 7 8 9 A B C D E F
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
Opcode Map
LSB of Opcode in Hexadecimal
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
Instruction Set
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 82 Freescale Semiconductor
Chapter 12 Electrical Specifications
12.1 Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Supply voltage Input voltage Normal operation Self-check mode (IRQ pin only) Current drain per pin (Excluding VDD and VSS) Storage temperature range Symbol VDD VIn VTST I TSTG Value -0.3 to +7.0 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 25 -65 to +150 Unit V V
mA C
NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 12.5 DC Electrical Characteristics for guaranteed operating conditions.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 83
Electrical Specifications
12.2 Operating Temperature
Characteristic Operating temperature range MC68HC05C9EP, FB MC68HC05C9ECP, CFB Symbol TA Value -40 to +105 Unit C
12.3 Thermal Characteristics
Characteristic Thermal resistance plastic dual in-line (PDIP) Thermal resistance quad flat pack (QFP) Symbol JA JA Value 60 95 Unit C/W C/W
VDD
R2 SEE TABLE TEST POINT C SEE TABLE R1 SEE TABLE
VDD = 4.5 V
Pins PA7-PA0 PB7-PB0 PC7-PC0 PD5-PD0, PD7 R1 3.26 R2 2.38 C 50 pF
VDD = 3.0 V
Pins PA7-PA0 PB7-PB0 PC7-PC0 PD5-PD0, PD7 R1 10.91 R2 6.32 C 50 pF
Figure 12-1. Test Load
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 84 Freescale Semiconductor
Power Considerations
12.4 Power Considerations
The average chip-junction temperature, TJ, in C, can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction to ambient, C/W PD = PINT + PI/O PINT = IDD x VDD watts (chip internal power) PI/O = Power dissipation on input and output pins (user determined) For most applications, PI/O PINT and can be neglected. The following is an approximate relationship between PD and TJ (neglecting PJ): PD = K / (TJ + 273C) Solving equations (1) and (2) for K gives: K = PD x (TA + 273C) + JA x (PD)2 where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (3) (2) (1)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 85
Electrical Specifications
12.5 DC Electrical Characteristics
Characteristic(1) (2) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.8 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP, PD7, PD0 (ILoad = -1.6 mA) PD5-PD1 (ILoad = -5.0 mA) PC7 Output low voltage (ILoad = 1.6 mA) PA7-PA0, PB7-PB0, PC6-PC0, PD7, PD5-PD0, TCMP (ILoad = 10 mA) PC7 Input high voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Input low voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Supply current (4.5-5.5 Vdc @ fOP = 2.1 MHz) Run(3) Wait(4) Stop(5) 25C -40 to +105C I/O ports hi-z leakage current PA7-PA0, PB7-PB0 (without pullup) PC7-PC0, PD7, PD5-PD0 Input current RESET, IRQ, OSC1, TCAP, PD7, PD5-PD0 Input pullup current(6) PB7-PB0 (with pullup) Capacitance Ports (as input or output) RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0 1. 2. 3. IDD -- -- -- -- 3.5 1.0 1.0 7.0 5.25 3.25 20.0 50.0 mA mA A A A A A Symbol VOL VOH Min -- VDD-0.1 Typ Max Unit
-- --
0.1 --
V
VOH
VDD-0.8 VDD-0.8 VDD-0.8
-- -- --
-- -- --
V
VOL -- -- VIH 0.7 x VDD -- -- -- 0.6 0.6 VDD
V
V
VIL
VSS
--
0.2 x VDD
V
IOZ
--
1.0
10
IIn IIn
-- 5
0.5 --
1 60
COut CIn
-- --
-- --
12 8
pF
VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +105C, unless otherwise noted Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25C only. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V 6. Input pullup current measured with VIL = 0.2 V
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 86 Freescale Semiconductor
DC Electrical Characteristics
VDD = 5.5 V T = -40 to 85 5.00 mA
)ID NG TI A ER
D
4.00 mA SUPPLY CURRENT (IDD)
N RU
P (O
3.00 mA
IT WA
I DD
2.00 mA
1.00 mA
50 mA
STOP IDD
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL / 2)
Figure 12-2. Maximum Supply Current versus Internal Clock Frequency, VDD = 5.5 V
VDD = 3.6 V T = -40 to 85
AT IN G) ID RU N( OP ER
TID AI W
D
1.50 mA
SUPPLY CURRENT (IDD)
1.00 mA
500 mA
STOP IDD 0.5 MHz 1.0 MHz
Figure 12-3. Maximum Supply Current versus Internal Clock Frequency, VDD = 3.6 V
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 87
D
Electrical Specifications
12.6 Control Timing
Characteristic(1) Frequency of operation Crystal External clock Internal operating frequency (fOSC / 2) Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width Symbol Min Max Unit
fOSC
-- dc
2.1 2.1
MHz
fOP tcyc tOXOV tILCH tRL tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL
-- dc 480 -- -- 1.5
2.1 2.1 -- 100 100 --
MHz ns ms ms tcyc tcyc ns tcyc ns tcyc ns
4.0 125
(3)
-- -- -- -- -- --
125
(4)
90
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +105C, unless otherwise noted 2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution. 3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. 4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC.
tTLTL(1) TCAP PIN 1. Refer to timer resolution data in 12.6 Control Timing.
tTH(1)
tTL(1)
Figure 12-4. TCAP Timing Relationships
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 88 Freescale Semiconductor
Control Timing
tILIL IRQ PIN tILIH
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz) or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 19 tCYC cycles.
NORMALLY USED WITH WIRED-OR CONNECTION
IRQ1 . . . IRQN
tILIH
IRQ (INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt is recognized.
Figure 12-5. External Interrupt Timing
OSC(1) tRL RESET tILIH IRQ(2) 4064 tCYC IRQ(3)
INTERNAL CLOCK
$3FFE Notes: 1. Represents the internal clocking of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level- and edge-sensitive mask option 4. RESET vector address shown for timing example
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF4
RESET OR INTERRUPT VECTOR FETCH
Figure 12-6. Stop Recovery Timing Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 89
Electrical Specifications
NOTE 1 VDD
OSC1 PIN(2) 4064 tCYC INTERNAL CLOCK(3)
INTERNAL ADDRESS BUS(3)
$3FFE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
INTERNAL DATA BUS(3) NOTE 4
NEW PCH
NEW PCL
RESET PIN
Notes: 1. Power-on reset threshold is typically between 1 V and 2 V. 2. OSC1 line is meant to represent time only, not frequency. 3. Internal clock, internal address bus, and internal data bus are not available externally. 4. RESET outputs VOL during 4064 POR cycles.
Figure 12-7. Power-On Reset Timing Diagram
INTERNAL CLOCK(1)
INTERNAL ADDRESS BUS(1)
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
NEW PC
INTERNAL DATA BUS(1) RESET(2) tRL
NEW PCH
NEW PCL
OP CODE
Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-8. External Reset Timing
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 90 Freescale Semiconductor
Serial Peripheral Interface Timing
12.7 Serial Peripheral Interface Timing
No. Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time (time to data active from high-impedance state) Slave disable time (hold time to high-impedance state) Data Valid Master (before capture edge) Slave (after enable edge)(3) Data hold time (outputs) Master (after capture edge) Slave (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Characteristic(1) Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(M) tLead(S) tLag(M) tLag(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 480 Note(2) 240 Note(2) 720 340 190 340 190 100 100 100 100 0 -- 0.25 -- 0.25 0 -- -- -- -- Max 0.5 2.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 -- 240 -- -- 100 2.0 100 2.0 Unit fOP MHz tCYC ns ns
2
3
ns
4
ns
5
ns
6
ns
7
ns
8 9 10
ns ns tCYC(M) ns tCYC(M) ns ns s ns s
11
12
13
1. VDD = 5.0 Vdc 10%; VSS = 0 Vdc, TA = -40 to +105C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10 for timing diagrams. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 91
Electrical Specifications
SS INPUT
SS pin of master held high. 1 12 5 4 12 13 13 12
SCK (CPOL = 0) OUTPUT
NOTE
SCK (CPOL = 1) OUTPUT
NOTE
5 4 6 7 LSB IN 10 BITS 6-1 11 (ref) MASTER LSB OUT 12
MISO INPUT 10 (ref) MOSI OUTPUT 13
MSB IN 11 MASTER MSB OUT
BITS 6-1
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS INPUT
SS pin of master held high. 1 13 5 4 12 13 NOTE 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT 12 12 NOTE
SCK (CPOL = 0) OUTPUT
SCK (CPOL = 1) OUTPUT
5 4
MISO INPUT 10 (ref) MOSI OUTPUT 13
MSB IN 11 MASTER MSB OUT
BITS 6-1
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 12-9. SPI Master Timing Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 92 Freescale Semiconductor
Serial Peripheral Interface Timing
SS INPUT 1 SCK (CPOL = 0) INPUT 2 SCK (CPOL = 1) INPUT 8 MISO INPUT SLAVE 6 MOSI OUTPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 5 4 12 13 SLAVE LSB OUT 11 9 NOTE 5 4 13 12 3
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS INPUT 1 SCK (CPOL = 0) INPUT 2 SCK (CPOL = 1) INPUT 8 MISO OUTPUT 5 4 10 NOTE SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 10 BITS 6-1 12 BITS 6-1 11 LSB IN 13 9 SLAVE LSB OUT 5 4 3 13 12
Note: Not defined but normally LSB of character previously transmitted
a) SPI Slave Timing (CPHA = 1)
Figure 12-10. SPI Slave Timing Diagram
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 93
Electrical Specifications
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 94 Freescale Semiconductor
Chapter 13 Mechanical Specifications
13.1 Introduction
This section describes the dimensions of the plastic dual in-line package (DIP), and quad flat pack (QFP) MCU packages. Package dimensions available at the time of this publication are provided in this section. To make sure that you have the latest case outline specifications, contact one of the following: * Local Freescale Sales Office * World Wide Web at http://www.freescale.com Follow World Wide Web on-line instructions to retrieve the current mechanical specifications.
13.2 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03)
NOTES: 1. POSITION TOLERANCE OF LEADS (D), SHALL BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITIONS, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 1 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 1 0.020 0.040
40
21
B
1 20
A C N
L
J H G F D K
SEATING PLANE
M
DIM A B C D F G H J K L M N
Figure 13-1. 40-Pin Plastic DIP Package (Case 711-03)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 95
Mechanical Specifications
13.3 44-Lead Quad Flat Pack (QFP) (Case 824A-01)
L
33 34
23 22 S S
D
D
B -A,B,DB
S
0.20 (0.008) M C A-B 0.05 (0.002) A-B
-AL
-BB
V
DETAIL A
44 1 11 12
0.20 (0.008)
M
H A-B
S
DETAIL A
F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B
BASE METAL S
D
S
J
S
N D
D
S
M
DETAIL C
DATUM PLANE
0.20 (0.008)
M
C A-B
S
D
S
SECTION B-B CE -CSEATING PLANE
-HH
0.01 (0.004) G M M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.45 2.10 0.45 0.30 2.10 2.00 0.40 0.30 0.80 BSC 0.25 0.23 0.13 0.95 0.65 8.00 REF 10 5 0.17 0.13 7 0 0.30 0.13 12.95 13.45 0.13 0 12.95 13.45 0.40 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC 0.010 0.005 0.009 0.026 0.037 0.315 REF 10 5 0.005 0.007 7 0 0.005 0.012 0.510 0.530 0.005 0 0.510 0.530 0.016 0.063 REF
T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
Figure 13-2. 44-Lead QFP (Case 824A-01)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 96 Freescale Semiconductor
Chapter 14 Ordering Information
14.1 Introduction
This section contains ordering information for the available package types.
14.2 MC Order Numbers
Table 14-1 shows the MC order numbers for the available package types. Table 14-1. MC Order Numbers
Package Type 40-pin plastic dual in-line package (DIP) 44-pin quad flat pack (QFP) 1. P = Plastic dual in-line package (PDIP) 2. FB = Quad flat pack (QFP) Temperature Range -40C to 105C -40C to 105C Order Number MC68HC05C9ECP MC68HC05C9ECFB
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 97
Ordering Information
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 98 Freescale Semiconductor
Appendix A Self-Check Mode
A.1 Introduction
This appendix describes the self-check mode.Self-Check Mode Self-check mode is entered upon the rising edge of RESET if the IRQ pin is at Vtst and the TCAP pin is at logic 1.
A.2 Self-Check
The self-check read-only memory (ROM) at mask ROM location $3F00-$3FEF determines if the microcontroller unit (MCU) is functioning properly. These tests are performed: 1. Input/output (I/O) -- Functional test of ports A, B, and C 2. Random-access memory (RAM) -- Counter test for each RAM byte 3. Timer -- Test of counter register and OCF bit 4. Serial communications interface (SCI) -- Transmission test; checks for RDRF, TDRE, TC, and FE flags 5. ROM -- Exclusive OR with odd ones parity result 6. Serial peripheral interface (SPI) -- Transmission test; checks for SPIF and WCOL flags The self-check circuit is shown in Figure A-1.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 99
Self-Check Mode
V 10 V DD VDD
MC34064 4.7 k RESET 1 IRQ NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V DD MC68HC05C9A V 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DD
OSC1 OSC2 TCAP PD7 TCMP 10K PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3 PC4 PC5 PC6 330 330 330 PC7 330 V CMOS BUFFER (MC74HC125) 1 M V 10 M 20 pF 20 pF 4 MHz
DD
DD
Notes: 1. VDD = 5.0 V 2. TCMP = NC
Figure A-1. Self-Check Circuit Schematic
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 100 Freescale Semiconductor
Self-Check Results
A.3 Self-Check Results
Table A-1 shows the LED codes that indicate self-check test results. Table A-1. Self-Check Circuit LED Codes
PC3 Off Off Off Off Off Off PC2 On On On Off Off Off PC1 On Off Off On On Off PC0 Off On Off On Off On Remarks I/O failure RAM failure Timer failure SCI failure ROM failure SPI failure No failure Device failure
Flashing All others
Perform these steps to activate the self-check tests: 1. Apply 10 V (2 x VDD) to the IRQ pin. 2. Apply a logic 1 to the TCAP pin. 3. Apply a logic 0 to the RESET pin. The self-check tests begin on the rising edge of the RESET pin. RESET must be held low for 4064 cycles after power-on reset (POR), or for a time, tRL, for any other reset. For the value of tRL, see 12.7 Serial Peripheral Interface Timing and 12.6 Control Timing.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 101
Self-Check Mode
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 102 Freescale Semiconductor
Appendix B M68HC05Cx Family Feature Comparisons
Refer to Table B-1 for a comparison of the features for all the M68HC05C Family members.
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor 103
104
M68HC05Cx Family Feature Comparisons
Table B-1. M68HC05Cx Feature Comparison
C4 USER ROM USER EPROM CODE SECURITY RAM OPTION REGISTER (IRQ/RAM/ SEC) MASK OPTION REGISTER(S) PORTB KEYSCAN (PULLUP/ INTERRUPT) PC7 DRIVE 4160 -- NO 176 C4A 4160 -- YES 176 705C4A -- 4160 YES 176 $1FDF (IRQ/SEC) C8 7744 -- NO 176 C8A 7744 -- YES 176 705C8 -- 7596-7740 YES 176-304 $1FDF (IRQ/RAM/ SEC) NO 705C8A -- 7596-7740 YES 176-304 $1FDF (IRQ/RAM/SEC) C12 12,096 -- NO 176 C12A 12,096 -- YES 176 C9 15,760-15,936 -- NO 176-352 $3FDF (IRQ/RAM) C9A/C9E 15,760-15,936 -- YES 176-352 $3FDF (IRQ/RAM) 705C9 -- 15,760-15,936 NO 176-352 $3FDF (IRQ/RAM) 705C9A -- 12,096-15,936 YES 176-352 $3FDF (IRQ/RAM)
NO
NO
NO
NO
NO
NO
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1 Freescale Semiconductor
NO
NO YES MASK OPTION HIGH CURRENT
$1FF0-$1FF1 YES MOR SELECTABLE HIGH CURRENT
NO
NO YES MASK OPTION HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION 64 ms (@4 MHz OSC)
$1FF0-$1FF1 YES MOR SELECTABLE HIGH CURRENT PD7, 5-0 INPUT ONLY TWO TYPES SOFTWARE+ MOR SOFTWARE+ MOR SELECTABLE WRITE $55/$AA TO $001D OR CLR $1FF0 YES PROGRAMMABLE COP/CLOCK MONITOR NO
NO YES MASK OPTION HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION
NO YES MASK OPTION HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION
NO
NO YES MASK OPTION HIGH CURRENT
NO
$3FF0-$3FF1 YES MOR SELECTABLE HIGH CURRENT
NO
NO
NO
NO
NO
STANDARD
STANDARD
STANDARD PD7, 5-0 INPUT ONLY YES SOFTWARE SOFTWARE SELECTABLE
STANDARD PD7, 5-0 BIDIRECTIONAL YES SOFTWARE SOFTWARE SELECTABLE
STANDARD
PORT D COP COP ENABLE
PD7, 5-0 PD7, 5-0 PD7, 5-0 PD7, 5-0 INPUT ONLY INPUT ONLY INPUT ONLY INPUT ONLY NO -- YES MASK OPTION 64 ms (@4 MHz OSC) YES MOR 64 ms (@4 MHz OSC) NO --
PD7, 5-0 PD7, 5-0 PD7, 5-0 BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL YES SOFTWARE SOFTWARE SELECTABLE YES SOFTWARE SOFTWARE SELECTABLE TWO TYPES SOFTWARE+ MOR SOFTWARE+ MOR SELECTABLE WRITE $55/$AA TO $001D OR CLR $3FF0 YES (C9A MODE) POR/C9A COP/ CLOCK MONITOR MOR SELECTABLE (C12A MODE)
COP TIMEOUT
--
--
64 ms 64 ms (@4 MHz OSC) (@4MHz OSC)
COP CLEAR
--
CLR $1FF0
CLR $1FF0
--
CLR $1FF0
WRITE $55/$AA TO $001D
CLR $3FF0
CLR $3FF0
WRITE $55/$AA TO $001D
WRITE $55/$AA TO $001D
WRITE $55/$AA TO $001D
CLOCK MONITOR ACTIVE RESET
NO
NO
NO
NO
NO
YES
NO
NO
YES POR/COP/ CLOCK MONITOR
YES POR/COP/ CLOCK MONITOR
YES POR/COP/ CLOCK MONITOR
NO
NO
NO
NO
NO
COP/CLOCK MONITOR
NO
NO
STOP DISABLE
NO
MASK OPTION
NO
NO
MASK OPTION
NO
MASK OPTION
MASK OPTION
NO
NO
NO
Notes: 1. The expanded RAM map (from $30-$4F and $100-$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A. 2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.
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MC68HC05C9E Rev. 0.1, 9/2005

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